CS 493 – CA Lab Assignment 1

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PROBLEM STATEMENT

Write s VHDL program to implement AND, OR, NOT, NOR, NAND and XOR gate.

SOURCE CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity allgates is
Port ( a : in bit;
b : in bit;
c : out bit;
d : out bit;
e : out bit;
f : out bit;
g : out bit;
h : out bit);

end allgates;

architecture Behavioral of allgates is

begin
c<=a and b;
d<=a or b;
e<=not b;
f<=a nor b;
g<=a nand b;
h<=a xor b;

end Behavioral;

GRAPH

Download graph in color and grayscale in pdf format from this gdrive link : https://rebrand.ly/cs493asgn1

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