CS 493 – CA Lab Assignment 3

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PROBLEM STATEMENT

Write a VHDL program to design a Comparater.

SOURCE CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity asgn3comp is
Port ( a,b : in STD_LOGIC_VECTOR (3 downto 0);
equal,greater,less : out STD_LOGIC);
end asgn3comp;

architecture Behavioral of asgn3comp is

begin
comp:process(a,b) is
begin
if(a=b) then
equal<=’1′;
less<=’0′;
greater<=’0′;

elsif(a<b) then
equal<=’0′;
less<=’1′;
greater<=’0′;

else
equal<=’0′;

GRAPH

Download graph and rtl schematic diagram (black and white) in pdf and docx format from this gdrive link : https://rebrand.ly/cs492asgn3_4

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