CS 493 – CA Lab Assignment 3

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PROBLEM STATEMENT

Write s VHDL program to design a full adder.

SOURCE CODE

library IEEE;
use IEEE.STD_LOGIC_1164.ALL

entity full_adder is
Port ( a : in bit;
b : in bit;
c : in bit;
cout : out bit;
sout : out bit);

end full_adder;

architecture Behavioral of full_adder is

begin

sout<= a xor b xor c;
cout<= (a and b) or (b and c) or (c and a);

end Behavioral;

GRAPH

Download graph and rtl schematic diagram (black and white) in pdf and docx format from this gdrive link : https://rebrand.ly/cs493asgn2_3

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