CS 493 – CA Lab Assignment 4

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PROBLEM STATEMENT

Write a VHDL program to design a 4:1 MUX.

SOURCE CODE

library IEEE;
use IEEE.STD_LOGIC_1164.AL

entity asgn4 is
Port ( a,b,c,d : in STD_LOGIC;
sel : in STD_LOGIC_VECTOR (1 downto 0);
y : out STD_LOGIC);
end asgn4;

architecture Behavioral of asgn4 is

begin
y<=a when sel=”00″ else
b when sel=”01″ else
c when sel=”10″ else
d;

end Behavioral;

GRAPH

Download graph and rtl schematic diagram (black and white) in pdf and docx format from this gdrive link : https://rebrand.ly/cs492asgn3_4

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